The present invention relates to the field of electronic memories for data storage. More particularly, the present invention relates to ways of providing a memory with write enable information.
Digital information can be stored in various types of memories, including random access memories (xe2x80x9cRAMsxe2x80x9d), electrically erasable read-only memories (xe2x80x9cEEPROMsxe2x80x9d), flash memories, etc. Data is typically stored in a two-dimensional array in which one row of bits is accessed at a time.
A RAM is a volatile memory that can be erased and written to relatively quickly, but which loses its data when power is removed. A RAM can be either static (i.e., an xe2x80x9cSRAMxe2x80x9d) or dynamic (i.e., a xe2x80x9cDRAMxe2x80x9d). In an SRAM, once data is written to a memory cell, the data remains stored as long as power is applied to the chip, unless the same memory cell is written again. In a DRAM, the data stored in a memory cell must be periodically refreshed by reading the data and then writing it back again, or else the data in the cell disappears.
FIG. 1 shows a block diagram of a prior DRAM 10. DRAM 10 typically is part of a computer system that includes a high speed bus 19 and a DRAM controller. DRAM 10 includes DRAM array 11, which consists of one or more banks. For example, array 11 has Bank0 and Bank1. Interface 18 contains logic for processing and routing signals entering and leaving DRAM array 11. Signals enter and leave DRAM 10 on interface pins 6 which connect to bus 19. The number of pins making up interface pins 6 depends upon the width of bus 19 and also upon the bus protocol used by a computer system to which the DRAM is connected.
FIG. 2 shows how interface 18 communicates with Bank0 of array 11 of DRAM 10. Bank0 of array 11 can store xe2x80x9ctxe2x80x9d units of data. A unit of data can be a byte, and the byte is defined as being xe2x80x9csxe2x80x9d bits wide, where in this case xe2x80x9csxe2x80x9d is 8 bits or 9 bits (i.e., a X8 byte or a X9 byte). Address interface 60 provides column and row address signals 42 and 44. Data interfaces 51 through 53 transfer data to and from array bank 11 into and out of DRAM 10. Data to be read out of Bank0 of array 11 is carried on R lines 38, and data to be written to Bank0 of array 11 is carried on W lines 36. For example, data interface 51 provides for conveyance of data bits [txe2x88x921:0][0], these bits being the 0th bits of each of bytes 0 through txe2x88x921 of Bank0 of array 11, or all the 0th bits of the bytes to be transferred. Similarly, data interface 52 carries all the 1th bits of Bank0 of array 11.
Write enable (xe2x80x9cWExe2x80x9d) interface 56 provides a WE signal for each byte of data of Bank0 of array 11. Signals WE[txe2x88x921:0] are WE signals for byte 0 through byte txe2x88x921. The WE signals are carried on WE lines 34. A WE signal indicates whether an associated byte is to be written or not written during a write operation.
Control interface 58 provides the following signals: column access strobe (xe2x80x9cCASxe2x80x9d) 62, row access strobe (xe2x80x9cRASxe2x80x9d) 64, and Read/Write (xe2x80x9cW/Rxe2x80x9d) signal 66. RAS and CAS are timing signals indicating a row or column access. W/R 66 specifies whether an operation is a write operation or a read operation
FIG. 3 shows the types of inputs to prior DRAMs. Various types of prior DRAMs have provided various separate pins for the following inputs: row address 74, column address 76, read and write data 78, a write/read input signal 82, the RAS 84, the CAS 86, and write enable signals 80. Having separate pins for each of these inputs to the DRAM is relatively inefficient because the pins take up space and not all of the signals overlap in time.
For DRAMs using different signals that are not active at the same point in time, several prior methods have been used to permit the sharing of pins, however. The sharing of pins minimizes the pin count without adversely affecting functionality.
One prior method for conserving DRAM interface pins is columnn/row address multiplexing. FIG. 4 illustrates column and row address multiplexing. FIG. 4 shows that one column and row address pin Arc[Nrc-1:0] 92 handles column and row address inputs 76 and 74 of FIG. 3. This is possible because column and row address signals are not active at the same time.
Another prior method is data in/out multiplexing. Data to be read and written is multiplexed onto the same pins of a DRAM. This is also referred to as Write/Read multiplexing or W/R multiplexing. FIG. 5 illustrates W/R multiplexing, in which data read from or written to a DRAM uses the same pins 102 for communicating with the exterior of the DRAM. Data is not read from and written to a DRAM at the same time, and thus it is possible to share data pins.
FIG. 6 illustrates another prior method of bit multiplexing, called data byte multiplexing. For data byte multiplexing, xe2x80x9ctxe2x80x9d data bits are transferred in serial over the same pin. For one prior art scheme, xe2x80x9ctxe2x80x9d equals 8. Each data bit is from a different byte. This is possible in prior DRAMs in which the internal RAM cycle rate, sometimes referred to as Columnn Access Strobe (xe2x80x9cCASxe2x80x9d) cycle rate, is slower than the DRAM input/output (xe2x80x9cI/Oxe2x80x9d) cycle rate.
For the example shown in FIG. 6, the I/O cycle rate is xe2x80x9ctxe2x80x9d times faster than the CAS cycle rate. Thus, if a block of data is xe2x80x9ctxe2x80x9d bytes, and one bit of each byte is to be transferred in a CAS cycle, then only one pin per xe2x80x9ctxe2x80x9d bits is needed during one CAS cycle for data transfer. For these reasons pins 202 can replace pins 102 of FIG. 5, and the number of data pins is reduced by a factor of xe2x80x9ct.xe2x80x9d
In FIG. 7, another prior bit multiplexing method is shown. This method is used in typical prior DRAM systems in which row address signals and data signals are not transferred at the same time. Pins 302 transmit read and write data, but also carry row address signals 44, thus eliminating the need for pins 74 of FIG. 3. The column address requires dedicated column address pins 76 because column address information can be transferred at the same time data is transferred.
For the above described prior methods, dedicated WE pins are required. In prior memories in which WE signals travel a longer path to DRAM array 11 then do data signals, dedicated registers are required to hold data during the wait for WE signals. The WE signals indicate whether the data is to be written or not written to DRAM array 11.
FIG. 8A shows a prior art memory configuration using RDRAMs(copyright) (xe2x80x9cRambus DRAMsxe2x80x9d) of Rambus, Inc. of Mountain View, Calif. FIG. 8B shows how WE information is multiplexed for that Rambus memory configuration. As shown in FIG. 8B, eight eight-bit wide WE words comprising WE block 981 are transmitted into a RDRAM over the nine-bit wide data bus and enter the RDRAM through pins BusData[7] through BusData[0] of data pins 980. The ninth data pin, pin BusData[8], is not used for transmission of the WE words. The WE words are stored in registers of the RDRAM. Each WE word is associated with a respective one of eight data blocks. Each data block is eight bytes long. Each data byte is also referred to as a data word. Each bit of each of the WE words is associated with a respective one of the eight data bytes in the respective block, which are each eight bits wide and are sent over the data bus and to the data pins of the RDRAM. Each bit of the WE word determines whether or not the associated data byte is written to the RDRAM. For example, the first WE word in WE block 981 pertains to DataBlock 0. Bit 0 of the first WE word determines whether data byte 1000 is written. Bit 1 of the first WE word determines whether data byte 1001 is written, and so on. Similarly, each WE word pertains to a data block until the final WE word of WE block 981 determines whether data bytes in DataBlock 7 are written. For this prior art scheme, a single clock cycle has two phases, allowing two transfer operations to occur within a single clock cycle.
One disadvantage of this prior method is that 64 registers are needed to hold the 64 WE bits during the time the write operation is taking place. Another disadvantage of the prior method is that a WE block must be transmitted for every group of eight data blocks that are transmitted. The periodic transmission of WE blocks takes time and therefore reduces bandwidth otherwise available for data transmission.
Prior DRAM memory systems have included some method of detecting errors in stored data. For one of these methods a type of data bit called an Error Detection and Correction (xe2x80x9cEDCxe2x80x9d) bit is used. An EDC bit can be either a parity bit or an error correction code (xe2x80x9cECCxe2x80x9d) bit. Parity is a basic prior method of error detection without error correction. A parity bit is associated with a byte of data and indicates whether or not one of the bits in the byte is erroneous. One prior art scheme uses a ninth bit out of a X9 byte as the parity bit. Parity is said to be either odd or even (indicated by an exclusive-OR or exclusive-NOR operation). If a parity check reveals that the state of the parity bit is inconsistent with the state of the other bits of the data byte, a parity error is detected. When a parity error is detected, the system is typically restarted.
An ECC scheme is a more sophisticated prior EDC method. Single ECC bits do not refer to a single byte of data, as is typically the case with a parity bit. Rather, multiple ECC bits are combined to form a word that encodes complex error detection and correction information. ECC words of various widths are required to encode information for blocks of data of various sizes (a block having xe2x80x9ctxe2x80x9d units of data, each unit being xe2x80x9csxe2x80x9d bits wide). According to a prior ECC technique a word of width LOG2 (N bits/block)+2 is required to encode ECC data for a block of size N bits. With the use of ECC it is possible to both detect and correct bit errors.
The choice of which EDC scheme is used can affect DRAM performance in prior DRAM systems. When an ECC scheme is chosen, write time may be increased and performance reduced. This is true because ECC bits do not refer to a single data byte, but form part of an ECC word referring to the entire block. Thus, when it is desired to write only a portion of the block, the ECC word for the entire block will change in complex ways such that it no longer reflects accurate information about the block. This makes it necessary for every partial write to the block to involve reading out the entire block, modifying it in part so that the ECC can be reformulated, and writing the block back again. This process is called a Read/Modify/Write, or R/M/W. R/M/Ws cost extra time and are preferably avoided. If ECC is used and the entire block is written, however, the R/M/Ws are not required.
If parity is chosen, it is possible to benefit from using a Write Enable (xe2x80x9cWExe2x80x9d) signal associated with a single X9 byte to indicate whether the byte is to be written or not written. For certain prior DRAMs, separate WE pins convey WE signals associated with each X9 byte of the block of data. Because parity bits refer only to the X9 byte they are part of, the parity bits will be changed appropriately when a X9 byte is written, and unwritten parity bits will be unaffected. Thus, with the use of parity and WE, it is not necessary to perform R/M/Ws when writing to the memory.
One object of the present invention is to provide a memory with write enable information, yet minimizing the circuit area required and maximizing performance.
Another object of the present invention is to reduce the number of memory pins required without adversely affecting memory functionality.
Another object is to reduce memory register resources required, thereby reducing memory die size.
Another object is to allow for faster memory operation.
Another object is to allow the use of write enable and error correction and detection in a memory without the requirement of a pin dedicated solely to the write enable function.
A method is described for providing a memory with a serial sequence of write enable signals that are offset in time with respect to respective data received by a plurality of data inputs of the memory.
A memory is also described with an array for data storage, a plurality of data input pins, and a separate pin for receiving either additional data or a serial sequence of write enable signals applicable to data received by the plurality of data input pins. The additional data that the separate pin receives could, for example, be error detection and correction (EDC) information. A method is also described for multiplexing write enable information and error detection and correction information.
Other objects, features, and advantages of the present invention will be apparent from the accompanying drawings and from the detailed description that follows below.